Bounding of switching activity in logic circuits
Abstract (summary)
The thesis presents algorithms, implementation, and results of a new method based on constraint resolution for finding an upper bound on switching activity in the combinational part of a synchronous sequential circuit. The obtained switching activity is the major component for computing circuit power consumption (peak power) and several reliability parameters (e.g., voltage drops in power busses, electromigration). It is a static (input-pattern independent) method. The constraint system representing the circuit is built of constraints defined by gates and the operating environment of the circuit. The variables of the constraint system are all possible waveforms abstracted into four classes and expressed as sets of transitions for each unit of discrete time. The constraints of the constraint system are derived from the gates. Each gate is translated into a projection function which constrains each of its terminals based on the values on all other terminals independently of the netlist distinction between gate inputs and outputs. The method rapidly computes an upper bound on the switching activity. The bound is further tightened by case analysis.
Two major techniques were used to capture a global picture of the circuit and use this acquired information to speed up or improve the analysis. They are reconvergent region analysis and global learning.
The method has two major applications: estimation of peak power and estimation of peak current. Both application were tested with our C++ implementation on ISCAS'85 benchmark circuits and the quality of the results for different heuristics was compared. The results show that each heuristic is more suitable for a different type of circuit. The method was also compared with exhaustive simulation on a set of MCNC circuits.
The current implementation supports the fixed gate delay model and shares most of the code with a timing verification method based on constraint resolution. The performance is further improved by a parallel implementation of the case analysis on a network of inexpensive workstations. Our C++ implementation shows speedup of 8 on a homogeneous network of 10 workstations, and 47 on a heterogeneous network of 87 workstations. (Abstract shortened by UMI.)
Indexing (details)
Electrical engineering
0544: Electrical engineering